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hm538123b series 1 m vram (128-kword 8-bit) ade-203-231d (z) rev. 4.0 nov. 1997 description the hm538123b is a 1-mbit multiport video ram equipped with a 128-kword 8-bit dynamic ram and a 256-word 8-bit sam (ser ial access memory). its ram and sam oper ate independently and asynchronously. it can transfer data between ram and sam. in add ition, it has two modes to realize fast writing in ram. block write and flash write modes clear the data of 4-word 8-bit and the data of one row (256-word 8-bit) respectively in one cycle of ram. and the hm538123b makes split transfer cycle possible by dividing sam into two sp lit buffers equipped with 128-word 8-bit each. this cycle can transfer data to sam which is not active, and enables a continuous serial access. features multiport organization asynchronous and simultaneous operation of ram and sam capability ? ram: 128-kword 8-bit and ? sam: 256-word 8-bit access time ? ram: 60 ns/70 ns/80 ns/100 ns max ? sam: 20 ns/22 ns/25 ns/25 ns max cycle time ? ram: 125 ns/135 ns/150 ns/180 ns min ? sam: 25 ns/25 ns/30 ns/30 ns min low power ? active ram: 413 mw max sam: 275 mw max ? standby 38.5 mw max high-speed page mode capability mask write mode capability bidirectional data transfer cycle between ram and sam capability split transfer cycle capability block write mode capability flash write mode capability
hm538123b series 2 3 variations of refresh (8 ms/512 cycles) ? 5$6 -only refresh ? &$6 -before- 5$6 refresh ? hidden refresh ttl compatible ordering information type no. access time package hm538123bj-6 hm538123bj-7 hm538123bj-8 HM538123BJ-10 60 ns 70 ns 80 ns 100 ns 400-mil 40-pin plastic soj (cp-40d)
hm538123b series 3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 v si/o7 si/o6 si/o5 si/o4 se i/o7 i/o6 i/o5 i/o4 v dsf nc cas qsf a0 a1 a2 a3 a7 sc si/o0 si/o1 si/o2 si/o3 dt/oe i/o0 i/o1 i/o2 i/o3 v we nc ras nc a8 a6 a5 a4 v cc cc ss ss (top view) hm538123bj series pin description pin name function a0 C a8 address inputs i/o0 C i/o7 ram port data inputs/outputs si/o0 C si/o7 sam port data inputs/outputs 5$6 row address strobe &$6 column address strobe :( write enable '7 / 2( data transfer/output enable sc serial clock 6( sam port enable dsf special function input flag qsf special function output flag v cc power supply v ss ground nc no connection
hm538123b series 4 block diagram a0 ?a8 a0 ?a7 a0 ?a8 si/o0 ?si/o7 i/o0 ?i/o7 ras cas dt/oe we dsf sc se timing generator output buffer input buffer mask register input data control serial output buffer serial input buffer column decoder sense amplifier & i/o bus sam i/o bus sam column decoder data register serial address counter refresh counter row address buffer column address buffer row decoder memory array data register transfer gate transfer gate 0 255 511 0 flash write control block write control color resister address mask register qsf
hm538123b series 5 pin functions 5$6 5$6 (input pin): 5$6 is a basic ram signal. it is active in low level and standby in high level. row address and signals as shown in table 1 are input at the falling edge of 5$6 . the input level of these signals determine the operation cycle of the hm538123b. table 1 operation cycles of the hm538123b input level at the falling edge of 5$6 5$6 &$6 &$6 '7 '7 / 2( 2( :( :( 6( 6( dsf dsf at the falling edge of &$6 &$6 operation mode l x x x x cbr refresh h l l l l x write transfer h l l h l x pseudo transfer h l l x h x split write transfer h l h x l x read transfer h l h x h x split read transfer h h l x l l read/mask write h h l x l h mask block write h h l x h x flash write h h h x l l read/write h h h x l h block write h h h x h x color register read/write note: x; dont care &$6 &$6 (input pin): column address and dsf signal are f etched into chip at the falling edge of &$6 , which determines the operation mode of hm538123b. &$6 controls output impedance of i/o in ram. a0 C a8 (input pins): row address (ax0 C ax8) is determined by a0 C a8 level at the falling edge of 5$6 . column address (ay0 C ay7) is determined by a0 C a7 level at the falling edge of &$6 . in transfer cycles, row address is the address on the word line which transfers data with sam d ata register, and column address is the sam start address after transfer. :( :( (input pin): :( pin has two functions at the falling edge of 5$6 and after. when :( is low at the falling edge of 5$6 , the hm538123b turns to mask write mode. according to the i/o level at the time, write on each i/o can be masked. ( :( level at the falling edge of 5$6 is dont care in read cycle.) when :( is high at the falling edge of 5$6 , a normal write cycle is executed. after that, :( switches read/write cycles as in a standard dram. in a transfer cycle, the direction of transfer is determined by :( level at the falling edge of 5$6 . when :( is low, data is transferred from sam to ram (d ata is written into ram), and when :( is high, data is transferred from ram to sam (data is read from ram).
hm538123b series 6 i/o0 C i/o7 (input/output pins): i/o pins function as mask data at the falling edge of 5$6 (in mask write mode). data is written only to high i/o pins. data on low i/o pins are masked and internal data are retained. after that, they function as input/output pins as those of a standard dram. in block write cycle, they function as address mask data at the falling edge of &$6 . '7 '7 / 2( 2( (input pin): '7 / 2( pin functions as '7 (data transfer) pin at the falling edge of 5$6 and as 2( (output enable) pin after that. when '7 is low at the falling edge of 5$6 , this cycle becomes a transfer cycle. when '7 is high at the falling edge of 5$6 , ram and sam operate independently. sc (input pin): sc is a basic sam clock. in a ser ial read cycle, data outputs from an si/o pin synchronously with the rising edge of sc. in a serial write cycle, data on an si/o pin at the rising edge of sc is fetched into the sam data register. 6( 6( (input pin): 6( pin activates sam. when 6( is high, si/o is in the high impedance state in serial read cycle and data on si/o is not fetched into the sam d ata register in serial write cycle. 6( can be used as a mask for serial write because internal pointer is incremented at the rising edge of sc. si/o0 C si/o7 (input/output pins): si/os are input/output pins in sam. dir ection of input/output is determined by the previous transfer cycle. when it was a read transfer cycle, si/o outputs data. when it was a pseudo transfer cycle or write transfer cycle, si/o inputs data. dsf (input pin): dsf is a sp ecial function data input flag pin. it is set to high at the falling edge of 5$6 when new functions such as color register read/write, split transfer, and flash write, are used. dsf is set to high at the falling edge of &$6 when block write is executed. qsf (output pin): qsf outputs d ata of address a7 in sam. qsf is sw itched from low to high by accessing address 127 in sam and from high to low by accessing 255 address in sam.
hm538123b series 7 operation of hm538123b ram read cycle ( '7 / 2( high, &$6 high and dsf low at the f alling edge of 5$6 , dsf low at the f alling edge of &$6 ) row address is entered at the 5$6 falling edge and column address at the &$6 falling edge to the device as in standard dram. then, when :( is high and '7 / 2( is low while &$6 is low, the selected address data outputs through i/o pin. at the falling edge of 5$6 , '7 / 2( and &$6 become high to distinguish ram read cycle from transfer cycle and cbr refresh cycle. address access time (t aa ) and 5$6 to column address delay time (t rad ) specifications are added to enable high-speed page mode. ram write cycle (early write, delayed write, read-modify-write) ( '7 / 2( high, &$6 high and dsf low at the falling edge of 5$6 , dsf low at the falling edge of &$6 ) normal mode write cycle ( :( high at the falling edge of 5$6 ) when &$6 and :( are set low after driving 5$6 low, a write cycle is executed and i/o data is written in the selected addresses. when all 8 i/os are written, :( should be high at the falling edge of 5$6 to distinguish normal mode from mask write mode. if :( is set low before the &$6 falling edge, this cycle becomes an early write cycle and i/o becomes in high impedance. data is entered at the &$6 falling edge. if :( is set low after the &$6 falling edge, this cycle becomes a delayed write cycle. data is input at the :( falling. i/o does not become high impedance in this cycle, so data should be entered with 2( in high. if :( is set low after t cwd (min) and t awd (min) after the &$6 falling edge, this cycle becomes a read- modify-write cycle and enables read/write at the same address in one cycle. in this cycle also, to avoid i/o contention, data should be input after reading data and driving 2( high. mask write mode ( :( low at the falling edge of 5$6 ) if :( is set low at the falling edge of 5$6 , the cycle becomes a mask write mode which writes only to selected i/o. whether or not an i/o is written depends on i/o level (mask data) at the falling edge of 5$6 . then the data is written in high i/o pins and masked in low ones and internal data is retained. this mask data is effective during the 5$6 cycle. so, in high-speed page mode, the mask data is retained during the page access.
hm538123b series 8 high-speed page mode cycle ( '7 / 2( high, &$6 high and dsf low at the falling edge of 5$6 ) high-speed page mode cycle reads/writes the data of the same row address at high speed by toggling &$6 while 5$6 is low. its cycle time is one third of the random read/write cycle. in this cycle, read, write, and block write cycles can be mixed. note that address access time (t aa ), 5$6 to column address delay time (t rad ), and access time from &$6 precharge (t acp ) are added. in one 5$6 cycle, 256-word memory cells of the same row address can be accessed. it is necessary to specify access frequency within t rasp max (100 s). color register set/read cycle ( &$6 high, '7 / 2( high, :( high and dsf high at the f alling edge of 5$6 ) in color register set cycle, color data is set to the internal color register used in flash write cycle or block write cycle. 8 bits of internal color register are provided at each i/o. this register is composed of static circuits, so once it is set, it retains the data until reset. color register set cycle is just as same as the usual write cycle except that dsf is set high at the f alling edge of 5$6 , and read, early write and delayed write cycle can be executed. in this cycle, hm538123b refreshs the row address fetched at the falling edge of 5$6 . flash write cycle ( &$6 high, '7 / 2( high, :( low and dsf high at the falling edge of 5$6 ) in a flash write cycle, a row of data (256-word 8-bit) is cleared to 0 or 1 at each i/o according to the data of color register mentioned before. it is also necessary to mask i/o in this cycle. when &$6 and '7 / 2( is set high, :( is low, and dsf is high at the f alling edge of 5$6 , this cycle starts. then, the row address to clear is given to row address and mask data is given to i/o. mask data is as same as that of a ram write cycle. high i/o is cleared, low i/o is not cleared and the internal data is retained. cycle time is the same as those of ram read/write cycles, so all bits can be cleared in 1/256 of the usual cycle time. (see figure 1.)
hm538123b series 9 ras cas address we dt/oe dsf i/o color register set cycle flash write cycle flash write cycle row xi xj *1 *1 color data set color register execute flash write into each i/o on row address xi using color resister. execute flash write into each i/o on row address xj using color resister. figure 1 use of flash write block write cycle ( &$6 high, '7 / 2( high and dsf low at the f alling edge of 5$6 , dsf high at the falling edge of &$6 ) in a block write cycle, 4 columns of data (4-word 8-bit) is cleared to 0 or 1 at each i/o according to the data of color register. column addresses a0 and a1 are disregarded. the data on i/os and addresses can be masked. i/o level at the falling edge of &$6 determines the address to be cleared. (see figure 2.) normal mode block write cycle ( :( high at the falling edge of 5$6 ) the data on 8 i/os are all cleared when :( is high at the falling edge of 5$6 . mask block write mode ( :( low at the falling edge of 5$6 ) when :( is low at the falling edge of 5$6 , hm538123b starts mask block write mode to clear the data on an optional i/o. the mask data is the same as that of a ram write cycle. high i/o is cleared, low i/o is not cleared and the internal data is retained. the mask data is available in the 5$6 cycle. in page mode block write cycle, the mask data is retained during the page access.
hm538123b series 10 color register set cycle block write cycle block write cycle row row column a2?7 row column a2?7 *1 *1 *1 *1 color data address mask address mask ras cas address we dt/oe dsf i/o *1 i/o mask data low: mask high: non mask address mask data low: mask high: non mask i/o0 i/o1 i/o2 i/o3 column0 (a0 = 0, a1 = 0) mask data column1 (a0 = 1, a1 = 0) mask data column2 (a0 = 0, a1 = 1) mask data column3 (a0 = 1, a1 = 1) mask data we low high i/o i/o mask data don't care non mask mask mode figure 2 use of block write transfer operation the hm538123b provides the read transfer cycle, split read transfer cycle, pseudo transfer cycle, write transfer cycle and split write transfer cycle as data transfer cycles. these transfer cycles are set by driving &$6 high and '7 / 2( low at the falling edge of 5$6 . they have following functions: (1) transfer data between row address and sam data register (except for pseudo transfer cycle) ? read transfer cycle and split read transfer cycle: ram to sam ? write transfer cycle and split write transfer cycle: sam to ram (2) determine si/o state (except for split read transfer cycle and split write transfer cycle) ? read transfer cycle: si/o output ? pseudo transfer cycle and write transfer cycle: si/o input (3) determine first sam address to access after transferring at column address (sam start address). sam start address must be d etermined by read transfer cycle or pseudo transfer cycle (split transfer cycle isnt available) before sam access, after power on, and determined for each transfer cycle.
hm538123b series 11 read transfer cycle ( &$6 high, '7 / 2( low, :( high and dsf low at the falling edge of 5$6 ) this cycle becomes read transfer cycle by driving '7 / 2( low, :( high and dsf low at the f alling edge of 5$6 . the row address data (256 8-bit) determined by this cycle is transferred to sam d ata register synchronously at the rising edge of '7 / 2( . after the rising edge of '7 / 2( , the new address data outputs from sam start address d etermined by column address. in read transfer cycle, '7 / 2( must be risen to transfer data from ram to sam. this cycle can access sam even during transfer (r eal time read transfer). in this case, the timing t sdd (min) specified between the last sam access before transfer and '7 / 2( rising edge and t sdh (min) specified between the first sam access and '7 / 2( rising edge must be satisfied. (see figure 3.) when read transfer cycle is executed, si/o becomes output state by first sam access. input must be set high impedance before t szs (min) of the first sam access to avoid data contention. ras cas address dt/oe sc si/o sam data before transfer sam data after transfer t sdd t sdh l xi yj yj yj + 1 dsf figure 3 real time read transfer pseudo transfer cycle ( &$6 high, '7 / 2( low, :( low, 6( high and dsf low at the f alling edge of 5$6 ) pseudo transfer cycle switches si/o to input state and set sam start address without data transfer to ram. this cycle starts when &$6 is high, '7 / 2( low, :( low, 6( high and dsf low at the f alling edge of 5$6 . data should be input to si/o later than t sid (min) after 5$6 becomes low to avoid data contention. sam access becomes enabled after t srd (min) after 5$6 becomes high. in this cycle, sam access is inhibited during 5$6 low, therefore, sc must not be risen.
hm538123b series 12 write transfer cycle ( &$6 high, '7 / 2( low, :( low, 6( low and dsf low at the falling edge of 5$6 ) write transfer cycle can transfer a row of data input by serial write cycle to ram. the row address of data transferred into ram is determined by the address at the falling edge of 5$6 . the column address is specified as the first address for serial write after terminating this cycle. also in this cycle, sam access becomes enabled after t srd (min) after 5$6 becomes high. sam access is inhibited during 5$6 low. in this period, sc must not be risen. data transferred to sam by read transfer cy cle or split read transfer cycle can be written to other addresses of ram by write transfer cycle. however, the address to write data must be the same as that of the read transfer cycle or the split read transfer cycle (row address ax8). figure 4 shows the example of row bit data transfer. in case ax8 is 0, data cannot be transferred ram address within the range of 100000000 to 111111111. same as the case of ax8 = 1. split read transfer cycle ( &$6 high, '7 / 2( low, :( high and dsf high at the falling edge of 5$6 ) to execute a continuous serial read by real time read transfer, hm538123b must satisfy sc and '7 / 2( timings and requires an external circuit to detect sam last address. sp lit read transfer cycle makes it possible to execute a continuous serial read without the above timing limitation. figure 5 shows the block diagram for a split transfer. sam d ata register (dr) consists of 2 split buffers, whose organizations are 128-word 8-bit each. let us suppose that data is read from upper data register dr1 (the row address ax8 is 0 and sam address a7 is 1.). when sp lit read transfer is executed setting row address ax8 0 and sam start addresses a0 to a6, 128-word 8-bit data are transferred from ram to the lower data register dr0 (sam address a7 is 0) auto matically. after data are read from data register dr1, data start to be read from sam start addresses of d ata register dr0. if the next split read transfer isnt executed while data are read from data register dr0, data start to be read from sam start address 0 of dr1 after d ata are read from data register dr0. if split read transfer is executed setting row address ax8 1 and sam start addresses a0 to a6 while data are read from data register dr1, 128-word 8-bit data are transferred to data register dr2. after data are read from data register dr1, data start to be read from sam start addresses of data register dr2. if the next split read transfer isnt executed while data is read from data register dr2, data start to be read from sam start address 0 of d ata register dr3 after data are read from data register dr2. in this time, sam d ata is the one transferred to data register dr3 finally while row address ax8 is 1. in split read data transfer, the sam start address a7 is automatically set in the data register which isnt used. the data on sam address a7, which w ill be accessed next, outputs to qsf, qsf is sw itched from low to high by accessing sam last address 127 and from high to low by accessing address 255. split read transfer cycle is set when &$6 is high, '7 / 2( is low, :( is high and dsf is high at the f alling edge of 5$6 . the cycle can be executed asyncronously with sc. however, hm538123b must be satisfied t sts (min) timing specified between sc rising and 5$6 falling. sam start address must be accessed, satisfying t rst (min), t cst (min) and t ast (min) timings specified between 5$6 or &$6 falling and column address. (see figure 6.) in split read transfer, si/o isnt switched to output state. therefore, read transfer must be executed to switch si/o to output state when the previous transfer cycle is pseudo transfer or write transfer cycle.
hm538123b series 13 a8 a0 000000000 100000000 011111111 111111111 (row address) ........ a8 a0 000000000 100000000 011111111 111111111 ........ possible impossible (read transfer cycle) (write transfer cycle) sam ram ram sam (row address) sam ram ram sam ........ figure 4 example of row bit data transfer memory array ax8 = 0 memory array dr1 sam i/o bus sam column decoder dr0 sam i/o bus dr3 dr2 sam i/o buffer si/o ax8 = 1 figure 5 block diagram for split transfer split write transfer cycle ( &$6 high, '7 / 2( low, :( low and dsf high at the falling edge of 5$6 ) a continuous serial write cannot be executed because accessing sam is inhib ited during 5$6 low in write transfer. split write transfer cycle makes it possible. in this cycle, t sts (min), t rst (min), t cst (min) and t ast (min) timings must be satisfied like split read transfer cycle. and it is impossible to switch si/o to input state in this cycle. if si/o is in output state, pseudo transfer cycle should be executed to switch si/o into input state. data transferred to sam by read transfer cy cle or split read transfer cycle can be written to other addresses of ram by split write transfer cycle. however, pseudo transfer cycle must be executed before split write transfer cycle. and the msb of row address (ax8) to write data must be the same as that of the read transfer cycle or the split read transfer cycle.
hm538123b series 14 ras cas address dt/oe dsf sc t (min) sts t (min) rst t (min) cst t (min) ast 255 (127) n (n + 127) 127 (255) 127 + yj (yj) yj xi figure 6 limitation in split transfer sam port operation serial read cycle sam port is in read mode when the previous d ata transfer cycle is read transfer cycle. access is synchronized with sc rising, and sam d ata is output from si/o. when 6( is set high, si/o becomes high impedance, and the internal pointer is incremented by the sc rising. after indicating the last address (address 255), the internal pointer indicates address 0 at the next access. serial write cycle if previous data transfer cycle is pseudo transfer cycle or write transfer cycle, sam port goes into write mode. in this cycle, si/o data is fetched into data register at the sc rising edge like in the serial read cycle. if 6( is high, si/o data isnt fetched into data register. internal pointer is incremented by the sc rising, so 6( high can be used as mask data for sam. after ind icating the last address (address 255), the internal pointer indicates address 0 at the next access.
hm538123b series 15 refresh ram refresh ram, which is composed of dynamic circuits, requires refresh to retain data. refresh is executed by accessing all 512 row addresses within 8 ms. there are three refresh cycles: (1) 5$6 -only refresh cycle, (2) &$6 -before- 5$6 (cbr) refresh cycle, and (3) hidden refresh cycle. besides them, the cycles which activate 5$6 such as read/write cycles or transfer cycles can refresh the row address. therefore, no refresh cycle is required when all row addresses are accessed within 8 ms. (1) 5$6 -only refresh cycle: 5$6 -only refresh cycle is executed by activating only 5$6 cycle with &$6 fixed to high after inputting the row address (= refresh address) from external circuits. to distinguish this cycle from data transfer cycle, '7 / 2( must be high at the falling edge of 5$6 . (2) cbr refresh cycle: cbr refresh cycle is set by activating &$6 before 5$6 . in this cycled, refresh address needs not to be input through external circuits because it is input through an internal refresh counter. in this cycle, output is in high impedance and power dissipation is lowered because &$6 circuits dont operate. (3) hidden refresh cycle: hidden refresh cycle executes cbr refresh with the data output by reactivating 5$6 when '7 / 2( and &$6 keep low in normal ram read cycles. sam refresh sam parts (data register, shift register and selector), organized as fully static circuitry, require no refresh. absolute maximum ratings parameter symbol value unit terminal voltage *1 v t C1.0 to +7.0 v power supply voltage *1 v cc C0.5 to +7.0 v short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c note: 1. relative to v ss .
hm538123b series 16 recommended dc operating conditions (ta = 0 to +70c) parameter symbol min typ max unit supply voltage *1 v cc 4.5 5.0 5.5 v input high voltage *1 v ih 2.4 6.5 v input low voltage *1 v il C0.5 *2 0.8 v notes: 1. all voltages referred to v ss 2. C3.0 v for pulse width 10 ns dc characteristics (ta = 0 to +70c, v cc = 5 v 10%, v ss = 0 v) hm538123b -6 -7 -8 -10 test conditions parameter symbol min max min max min max min max unit ram port sam port operating current i cc1 75706055ma 5$6 , &$6 cycling t rc = min sc = v il , 6( = v ih i cc7 125 120 100 95 ma 6( = v il , sc cycling t scc = min standby current i cc2 7 7 7 7 ma 5$6 , &$6 = v ih sc = v il , 6( = v ih i cc8 50504040ma 6( = v il , sc cycling t scc = min 5$6 -only refresh current i cc3 75706055ma 5$6 cycling &$6 = v ih t rc = min sc = v il , 6( = v ih i cc9 125 120 100 95 ma 6( = v il , sc cycling t scc = min page mode current i cc4 80807065ma &$6 cycling 5$6 = v il t pc = min sc = v il , 6( = v ih i cc10 130 130 110 105 ma 6( = v il , sc cycling t scc = min
hm538123b series 17 dc characteristics (ta = 0 to +70c, v cc = 5 v 10%, v ss = 0 v) (cont) hm538123b -6 -7 -8 -10 test conditions parameter symbol min max min max min max min max unit ram port sam port &$6 -before- 5$6 refresh current i cc5 50454035ma 5$6 cycling t rc = min sc = v il , 6( = v ih i cc11 100 95 80 75 ma 6( = v il , sc cycling t scc = min data transfer current i cc6 80756560ma 5$6 , &$6 cycling t rc = min sc = v il , 6( = v ih i cc12 130 125 105 100 ma 6( = v il , sc cycling t scc = min input leakage current i li C10 10 C10 10 C10 10 C10 10 a output leakage current i lo C10 10 C10 10 C10 10 C10 10 a output high voltage v oh 2.4 2.4 2.4 2.4 v i oh = C2 ma output low voltage v ol 0.4 0.4 0.4 0.4 v i ol = 4.2 ma notes: 1. i cc depends on output loading condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed once while 5$6 is low and &$6 is high. capacitance (ta = 25c, v cc = 5 v, f = 1 mhz, bias: clock, i/o = v cc , address = v ss ) parameter symbol min typ max unit address c i1 5 pf clock c i2 5 pf i/o, si/o, qsf c i/o 7 pf
hm538123b series 18 ac characteristics (ta = 0 to +70c, v cc = 5 v 10%, v ss = 0 v) *1,*16 test conditions input rise and fall time : 5 ns output load : see figures input pulse levels: v ss to 3.0 v input timing reference levels : 0.8 v, 2.4 v output timing reference levels : 0.8 v, 2.0 v i = ?2 ma oh i = 4.2 ma ol + 5 v i / o * 1 100 pf i = ?2 ma i = 4.2 ma ol + 5 v si / o * 1 50 pf oh output load (b) output load (a) note: 1. including scope & jig
hm538123b series 19 common parameter hm538123b -6 -7 -8 -10 parameter symbol min max min max min max min max uni t note s random read or write cycle time t rc 125 135 150 180 ns 5$6 precharge time t rp 55 55 60 70 ns 5$6 pulse width t ras 60 10000 70 10000 80 10000 100 10000 ns &$6 pulse width t cas 20 20 20 25 ns row address setup time t asr 0 0 0 0 ns row address hold time t rah 10 10 10 10 ns column address setup time t asc 0 0 0 0 ns column address hold time t cah 15 15 15 15 ns 5$6 to &$6 delay time t rcd 20 40 20 50 20 60 20 75 ns 2 5$6 hold time referenced to &$6 t rsh 20 20 20 25 ns &$6 hold time referenced to 5$6 t csh 60 70 80 100 ns &$6 to 5$6 precharge time t crp 10 10 10 10 ns transition time (rise to fall) t t 3 50 3 50 3 50 3 50 ns 3 refresh period t ref 8 8 8 8 ms '7 to 5$6 setup time t dts 0 0 0 0 ns '7 to 5$6 hold time t dth 10 10 10 10 ns dsf to 5$6 setup time t fsr 0 0 0 0 ns dsf to 5$6 hold time t rfh 10 10 10 10 ns dsf to &$6 setup time t fsc 0 0 0 0 ns dsf to &$6 hold time t cfh 15 15 15 15 ns data-in to &$6 delay time t dzc 0 0 0 0 ns4 data-in to 2( delay time t dzo 0 0 0 0 ns4 output buffer turn-off delay referred to &$6 t off1 20 20 20 20 ns 5 output buffer turn-off delay referred to 2( t off2 20 20 20 20 ns 5
hm538123b series 20 read cycle (ram), page mode read cycle hm538123b -6 -7 -8 -10 parameter symbol min max min max min max min max uni t note s access time from 5$6 t rac 60 70 80 100 ns 6, 7 access time from &$6 t cac 20 20 20 25 ns 7, 8 access time from 2( t oac 20 20 20 25 ns 7 address access time t aa 35 35 40 45 ns 7, 9 read command setup time t rcs 0 0 0 0 ns read command hold time t rch 0 0 0 0 ns10 read command hold time referenced to 5$6 t rrh 10 10 10 10 ns 10 5$6 to column address delay time t rad 15 25 15 35 15 40 15 55 ns 2 column address to 5$6 lead time t ral 35 35 40 45 ns column address to &$6 lead time t cal 35 35 40 45 ns page mode cycle time t pc 45 45 50 55 ns &$6 precharge time t cp 10 10 10 10 ns access time from &$6 precharge t acp 40 40 45 50 ns page mode 5$6 pulse width t rasp 6 0 100000 7 0 100000 8 0 100000 1 0 0 100000 n s
hm538123b series 21 write cycle (ram), page mode write cycle, color register set cycle hm538123b -6 -7 -8 -10 parameter symbol min max min max min max min max uni t note s write command setup time t wcs 0 0 0 0 ns11 write command hold time t wch 15 15 15 15 ns write command pulse width t wp 15 15 15 15 ns write command to 5$6 lead time t rwl 20 20 20 20 ns write command to &$6 lead time t cwl 20 20 20 20 ns data-in setup time t ds 0 0 0 0 ns12 data-in hold time t dh 15 15 15 15 ns 12 :( to 5$6 setup time t ws 0 0 0 0 ns :( to 5$6 hold time t wh 10 10 10 10 ns mask data to 5$6 setup time t ms 0 0 0 0 ns mask data to 5$6 hold time t mh 10 10 10 10 ns 2( hold time referred to :( t oeh 20 20 20 20 ns page mode cycle time t pc 45 45 50 55 ns &$6 precharge time t cp 10 10 10 10 ns &$6 to data-in delay time t cdd 20 20 20 20 ns 13 page mode 5$6 pulse width t rasp 6 0 100000 7 0 100000 8 0 100000 1 0 0 100000 n s
hm538123b series 22 read-modify-write cycle hm538123b -6 -7 -8 -10 parameter symbol min max min max min max min max uni t note s read-modify-write cycle time t rwc 175 185 200 230 ns 5$6 pulse width (read-modify- write cycle) t rws 110 10000 120 10000 130 10000 150 10000 ns &$6 to :( delay time t cwd 45 45 45 50 ns 14 column address to :( delay time t awd 60 60 65 70 ns 14 2( to data-in delay time t odd 20 20 20 20 ns 12 access time from 5$6 t rac 60 70 80 100 ns 6, 7 access time from &$6 t cac 20 20 20 25 ns 7, 8 access time from 2( t oac 20 20 20 25 ns 7 address access time t aa 35 35 40 45 ns 7, 9 5$6 to column address delay time t rad 15 25 15 35 15 40 15 55 ns read command setup time t rcs 0 0 0 0 ns write command to 5$6 lead time t rwl 20 20 20 20 ns write command to &$6 lead time t cwl 20 20 20 20 ns write command pulse width t wp 15 15 15 15 ns data-in setup time t ds 0 0 0 0 ns12 data-in hold time t dh 15 15 15 15 ns 12 2( hold time referred to :( t oeh 20 20 20 20 ns refresh cycle hm538123b -6 -7 -8 -10 parameter symbol min max min max min max min max uni t note s &$6 setup time ( &$6 -before- 5$6 refresh) t csr 10 10 10 10 ns &$6 hold time ( &$6 -before- 5$6 refresh) t chr 10 10 10 10 ns 5$6 precharge to &$6 hold time t rpc 10 10 10 10 ns
hm538123b series 23 flash write cycle, block write cycle hm538123b -6 -7 -8 -10 parameter symbol min max min max min max min max uni t note s &$6 to data-in delay time t cdd 20 20 20 20 ns 13 2( to data-in delay time t odd 20 20 20 20 ns 13 read transfer cycle hm538123b -6 -7 -8 -10 parameter symbol min max min max min max min max unit notes '7 hold time referenced to 5$6 t rdh 50 10000 60 10000 65 10000 80 10000 ns '7 hold time referenced to &$6 t cdh 20 20 20 25 ns '7 hold time referenced to column address t adh 25 25 30 30 ns '7 precharge time t dtp 20 20 20 30 ns '7 to 5$6 delay time t drd 65 65 70 80 ns sc to 5$6 setup time t srs 25 25 30 30 ns 1st sc to 5$6 hold time t srh 60 70 80 100 ns 1st sc to &$6 hold time t sch 25 25 25 25 ns 1st sc to column address hold time t sah 40 40 45 50 ns last sc to '7 delay time t sdd 5 5 5 5 ns last sc to '7 delay time t sdd2 25 25 25 25 ns 17 1st sc to '7 hold time t sdh 10 10 15 15 ns 5$6 to qsf delay time t rqd 65 70 75 85 ns 15 &$6 to qsf delay time t cqd 35 35 40 40 ns 15 '7 to qsf delay time t dqd 35 35 35 35 ns 15 qsf hold time referred to 5$6 t rqh 20 20 20 25 ns qsf hold time referred to &$6 t cqh 5 5 5 5 ns qsf hold time referred to '7 t dqh 5 5 5 5 ns serial data-in to 1st sc delay time t szs 0 0 0 0 ns serial clock cycle time t scc 25 25 30 30 ns
hm538123b series 24 read transfer cycle (cont) hm538123b -6 -7 -8 -10 parameter symbol min max min max min max min max uni t note s sc pulse width t sc 5 5 10 10 ns sc precharge time t scp 10 10 10 10 ns sc access time t sca 20 22 25 25 ns 15 serial data-out hold time t soh 5 5 5 5 ns serial data-in setup time t sis 0 0 0 0 ns serial data-in hold time t sih 15 15 15 15 ns 5$6 to column address delay time t rad 15 25 15 35 15 40 15 55 ns column address to 5$6 lead time t ral 35 35 40 45 ns 5$6 precharge to '7 high hold time t dthh 10 10 10 10 ns
hm538123b series 25 pseudo transfer cycle, write transfer cycle hm538123b -6 -7 -8 -10 parameter symbol min max min max min max min max uni t note s 6( setup time referred to 5$6 t es 0 0 0 0 ns 6( hold time referred to 5$6 t eh 10 10 10 10 ns sc setup time referred to 5$6 t srs 25 25 30 30 ns 5$6 to sc delay time t srd 20 20 25 25 ns serial output buffer turn-off time referred to 5$6 t srz 10 40 10 40 10 45 10 50 ns 5$6 to serial data-in delay time t sid 40 40 45 50 ns 5$6 to qsf delay time t rqd 65 70 75 85 ns 15 &$6 to qsf delay time t cqd 35 35 40 40 ns 15 qsf hold time referred to 5$6 t rqh 20 20 20 25 ns qsf hold time referred to &$6 t cqh 5 5 5 5 ns serial clock cycle time t scc 25 25 30 30 ns sc pulse width t sc 5 5 10 10 ns sc precharge time t scp 10 10 10 10 ns sc access time t sca 20 22 25 25 ns 15 6( access time t sea 20 22 25 25 ns 15 serial data-out hold time t soh 5 5 5 5 ns serial write enable setup time t sws 5 5 5 5 ns serial data-in setup time t sis 0 0 0 0 ns serial data-in hold time t sih 15 15 15 15 ns
hm538123b series 26 split read transfer cycle, split write transfer cycle hm538123b -6 -7 -8 -10 parameter symbol min max min max min max min max uni t note s split transfer setup time t sts 20 20 20 25 ns split transfer hold time referenced to 5$6 t rst 60 70 80 100 ns split transfer hold time referenced to &$6 t cst 20 20 20 25 ns split transfer hold time referenced to column address t ast 35 35 40 45 ns sc to qsf delay time t sqd 30 30 30 30 ns 15 qsf hold time referred to sc t sqh 5 5 5 5 ns serial clock cycle time t scc 25 25 30 30 ns sc pulse width t sc 5 5 10 10 ns sc precharge time t scp 10 10 10 10 ns sc access time t sca 20 22 25 25 ns 15 serial data-out hold time t soh 5 5 5 5 ns serial data-in setup time t sis 0 0 0 0 ns serial data-in hold time t sih 15 15 15 15 ns 5$6 to column address delay time t rad 15 25 15 35 15 40 15 55 ns column address to 5$6 lead time t ral 35 35 40 45 ns
hm538123b series 27 serial read cycle, serial write cycle hm538123b -6 -7 -8 -10 parameter symbol min max min max min max min max uni t note s serial clock cycle time t scc 25 25 30 30 ns sc pulse width t sc 5 5 10 10 ns sc precharge width t scp 10 10 10 10 ns access time from sc t sca 20 22 25 25 ns 15 access time from 6( t sea 20 22 25 25 ns 15 serial data-out hold time t soh 5 5 5 5 ns serial output buffer turn-off time referred to 6( t sez 20 20 20 20 ns 5 serial data-in setup time t sis 0 0 0 0 ns serial data-in hold time t sih 15 15 15 15 ns serial write enable setup time t sws 5 5 5 5 ns serial write enable hold time t swh 15 15 15 15 ns serial write disable setup time t swis 5 5 5 5 ns serial write disable hold time t swih 15 15 15 15 ns notes: 1. ac measurements assume t t = 5 ns. 2. when t rcd > t rcd (max) or t rad > t rad (max), access time is specified by t cac or t aa . 3. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition time t t is measured between v ih and v il . 4. data input must be floating before output buffer is turned on. in read cycle, read-modify-write cycle and delayed write cycle, either t dzc (min) or t dzo (min) must be satisfied. 5. t off1 (max), t off2 (max) and t sez (max) are defined as the time at which the output achieves the open circuit condition (v oh C 100 mv, v ol + 100 mv). 6. assume that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 7. measured with a load circuit equivalent to 2 ttl loads and 100 pf. 8. when t rcd 3 t rcd (max) and t rad t rad (max), access time is specified by t cac . 9. when t rcd t rcd (max) and t rad 3 t rad (max), access time is specified by t aa . 10. if either t rch of t rrh is satisfied, operation is guaranteed. 11. when t wcs 3 t wcs (min), the cycle is an early write cycle, and i/o pins remain in an open circuit (high impedance) condition. 12. these parameters are specified by the later falling edge of &$6 or :( . 13. either t cdd (min) or t odd (min) must be satisfied because output buffer must be turned off by &$6 or 2( prior to applying data to the device when output buffer is on. 14. when t awd 3 t awd (min) and t cwd 3 t cwd (min) in read-modify-write cycle, the data of the selected address outputs to an i/o pin and input data is written into the selected address. t odd (min) must be satisfied because output buffer must be turned off by 2( prior to applying data to the device. 15. measured with a load circuit equivalent to 2 ttl loads and 50 pf.
hm538123b series 28 16. after power-up, pause for 100 s or more and execute at least 8 initialization cycle (normal memory cycle or refresh cycle), then start operation. 17. after read transfer cycle, if split read transfer cycle is executed without sc access and sc address is 126 or 254, t sdd2 (min) must be satisfied 25 ns. except for those cases, t sdd (min) is effective and satisfied 5 ns. 18. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout timing waveforms *18 read cycle t rc t ras t csh t rcd t rsh t cas t ral t cal t cah t asc t rah t asr t rcs t cac t aa t rac t oac t dzc t dzo t dth t dts t fsr t rfh t fsc t cfh t cdd t off1 t off2 t rrh t rch t rp t crp ras cas address we i/o (output) dt/oe dsf i/o (input) row column t rad valid dout
hm538123b series 29 early write cycle t rc ras cas address we i/o (output) dt/oe dsf i/o (input) t ras t rp t crp t csh t rsh t cas t cah t asc t rah t asr t ws t wh t wcs t wch t dts t mh t ds t dh t ms t dth t fsr t fsc t rfh t cfh t rcd high-z *1 row column valid din mask data note: 1. this cycle becomes a normal mode write cycle when :( is high and a mask write cycle when :( is low. delayed write cycle ras cas address we i/o (output) dt/oe dsf i/o (input) row columun *1 valid din mask data t rc t ras t rp t crp t csh t rsh t rcd t cas t asr t rah t cah t rwl t cwl t wp t ws t wh t ms t mh t ds t dzc t dts t dth t fsr t rfh t fsc t cfh t oeh t dh t off2 t odd t asc note: 1. this cycle becomes a normal mode write cycle when :( is high and a mask write cycle when :( is low.
hm538123b series 30 read-modify-write cycle ras cas address we i/o (output) dt/oe dsf i/o (input) row column valid dout mask data t rwc valid din *1 t rws t rp t crp t rwl t cwl t wp t awd t cwd t rcs t ws t wh t cac t aa t rac t oac t dzc t mh t ms t off2 t odd t ds t dh t oeh t dts t dth t dzo t fsc t rfh t fsr t cfh t rad t rcd t asr t rah t asc t cah note: 1. this cycle becomes a normal mode write cycle when :( is high and a mask write cycle when :( is low. page mode read cycle ras cas address we i/o (output) dt/oe dsf i/o (input) t rc t rasp t rp t crp t rsh t cas t cp t pc t cp t rcd t csh t rad t cal t cah t rah t asr t rcs t rch t rcs t rcs t rch t cah t asc t cal t asc t ral t cal t cah t rrh t rch t cas t cas t aa t off1 t acp t cac t aa t acp t off1 t cdd t oac t dzc t cdd t oac t off2 t dzc t cdd t off2 t oac t dzc t dzo t dth t fsr t dts t rfh t fsc t cfh t fsc t cfh t fsc t cfh t rac t aa t cac t off1 t asc t cac row column column column valid dout valid dout valid dout
hm538123b series 31 page mode write cycle (early write) ras cas address we i/o (output) dt/oe dsf i/o (input) t rc t rasp t csh t cas t rcd t cp t cas t pc t cp t rsh t cas t crp t rp t cah t asc t cah t asc t cah t asc t rah t asr t ws t wh t wcs t wch t wcs t wch t wch t wcs t ds t dh t dh t ds t dh t ds t mh t ms t dts t dth t fsr t rfh t fsc t cfh t fsc t cfh t fsc t cfh row column column column *1 valid din valid din valid din mask data high-z note: 1. this cycle becomes a normal mode write cycle when :( is high and a mask write cycle when :( is low. page mode write cycle (delayed write) ras cas address we i/o (output) dt/oe dsf i/o (input) t rc t rasp t csh t rcd t cas t pc t cp t cas t cp t rsh t cas t rp t crp t cah t asc t rwl t cwl t wp t cwl t wp t cwl t wp t cah t asc t cah t asc t rah t asr t ws t wh t mh t ms t dts t fsr t rfh t cfh t fsc t fsc t cfh t fsc t cfh t oeh t dh t ds t dh t ds t dh t ds row column column column *1 mask data valid din valid din valid din note: 1. this cycle becomes a normal mode write cycle when :( is high and a mask write cycle when :( is low.
hm538123b series 32 5$6 5$6 -only refresh cycle ras cas address i/o (output) dt/oe dsf i/o (input) t rc t ras t rp t rpc t asr t rah t crp t cdd t off1 t off2 t odd t dts t dth t fsr t rfh row &$6 &$6 -before- 5$6 5$6 refresh cycle ras cas address i/o (output) dt/oe dsf t rc t ras t rp t rpc t csr t chr t rp t rpc t csr t cp t off1 high-z we inhibit falling transition
hm538123b series 33 hidden refresh cycle ras cas address i/o (output) dt/oe dsf i/o (input) t rc we t ras t rcd t rsh t ral t rad t asr t asc t cah t rcs t rrh t cac t aa t chr t ras t rp t rc t rp t crp t off1 t off2 t dzc t oac t dzo t dth t dts t fsr t rfh t fsc t cfh t rah row column t rac valid dout color register set cycle (early write) ras cas address we i/o (output) dt/oe dsf i/o (input) t rc t ras t rp t crp t csh t rsh t rcd t cas t rah t asr t ws t wh t wcs t wch t dh t ds t dts t dth t rfh t fsr color data row high-z
hm538123b series 34 color register set cycle (delayed write) ras cas address we i/o (output) dt/oe dsf i/o (input) t rc t ras t csh t rcd t rp t crp t cas t rsh t asr t rah t ws t dts t fsr t rfh t oeh t ds t dh t cwl t rwl t wp color data row high-z color register read cycle t rc t ras t csh t rcd t rsh t cas t asr t rah t wh t ws t rcs t rp t crp t rrh t rch t cdd t off1 t odd t off2 t cac t rac t dzc t oac t dzo t dth t dts t fsr t rfh ras cas address we i/o (output) i/o (input) dt/oe dsf row valid out
hm538123b series 35 flash write cycle t ras ras cas address we i/o (output) i/o (input) dt/oe dsf t rc t rp t rcd t crp t asr t rah t wh t ws t cdd t off2 t odd t ms t dts t dth t mh t rfh t fsr high-z row mask data t off1 block write cycle t ras ras cas address we i/o (output) i/o (input) dt/oe dsf t rc t rp t crp t rsh t rcd t csh t crp t asr t rah t asc t cah t ws t wh t cdd t off1 t off2 t odd t ms t mh t dth t ds t dh t fsr t rfh t fsc t cfh t dts row column a2-a8 *1 i/o mask data address mask data high-z note: 1. this cycle becomes a normal mode write cycle when :( is high and a mask write cycle when :( is low.
hm538123b series 36 page mode block write cycle t rc ras cas address we i/o (output) dt/oe dsf i/o (input) t rasp t rp t rsh t cas t crp t cp t pc t cas t cp t cas t rcd t csh t asc t asc t asr t rah t cah t cah t ws t wh t ms t mh t ds t dh t ds t dh t ds t dh t asc t cah t fsc t cfh t cfh t fsc t cfh t fsc t dth t dts t fsr t rfh row *1 i/o mask column a2-a8 column a2-a8 column a2-a8 address mask address mask address mask high-z note: 1. this cycle becomes a normal mode write cycle when :( is high and a mask write cycle when :( is low.
hm538123b series 37 read transfer cycle (1) t rc t ras t csh t rcd t rsh t cas t cah t asc t ral t rad t asr t rah t wh t ws t dts t cdh t adh t rdh t drd t dtp t dthh t scc t scc t scc t scc t sdh t sc t scp t soh t sca t sca t soh t soh t sca t sdd2* t sca t soh previous row new row t rp ras cas address we i/o (output) dt/oe sc si/o (output) si/o (input) t soh valid sout valid sout valid sout valid sout high-z row sam start address t crp t fsr t rfh t cqd t cqh t rqh t rqd t dqd t dqh sam address msb qsf *1 qsf *2 sam address msb dsf valid sout t sdd 3 notes: 1. this qsf timing is referred when sc is risen once or more between the previous transfer cycle and &$6 falling edge of this cycle (qsf is switched by '7 rising). 2. this qsf timing is referred when sc isn't risen between the previous transfer cycle and &$6 falling edge of this cycle (qsf is switched by 5$6 or &$6 falling). 3. after read transfer cycle, if split read transfer cycle is executed without sc access and sc address is 126 or 254, t sdd2 (min) must be satisfied 25 ns. except for those cases, t sdd (min) is effective and satisfied 5 ns.
hm538123b series 38 read transfer cycle (2) t ras ras cas address we i/o (output) dt/oe dsf sc si/o (output) qsf si/o (input) t rc t rsh t cas t csh t rcd t rad t rah t asr t asc t cah t wh t ws t rp t crp t ral t dts t rfh t fsr t drd t dtp t srs t sc t sdh t scc t sc t scp t sca t scp t sca t soh t szs t dqd t dqh t sih t sis valid sout row sam start address high-z sam address msb valid sin t dthh inhibit rising transition t dth t sah t sch t srh t cqd t cqh t rqd t rqh
hm538123b series 39 pseudo transfer cycle ras cas address we i/o (output) dt/oe dsf se si/o (output) qsf si/o (input) sam address msb sc t rc t ras t rp t crp t rsh t cas t rcd t asr t rah t asc t cah t wh t ws t dts t fsr t dth t rfh t sez t eh t es t srs t sc t sca t soh t srz t sid t cqd t cqh t rqd t rqh t sis t sih t sis t sih t sws t srd t scp t scc t sc t scp valid sin valid sin row sam start address valid sout t csh high - z valid sout inhibit rising transition
hm538123b series 40 write transfer cycle ras cas address we i/o (output) dt/oe dsf se si/o (output) qsf si/o (input) sc t rc t ras t rp t crp t rsh t cas t rcd t asr t rah t asc t cah t wh t ws t dts t fsr t dth t rfh row sam start address t es t eh t srs t sws t sc t sih t sis t cqd t cqh t rqd t rqh t sws t srd t scp t scc t sc t scp t sis t sih t sis t sih high-z valid sin valid sin valid sin sam address msb t csh inhibit rising transition
hm538123b series 41 split read transfer cycle t rc ras cas address we i/o (output) dt/oe dsf se si/o (output) qsf si/o (input) sc t ras t rp t csh t rsh t rcd t cas t asc t rah t asr t ws t wh t off1 t dts t dth t fsr t rfh t rst t ast t cst t scc t sc t scp t sts t sqd t sqh t sqd t sqh sam address msb valid sout valid sout valid sout valid sout valid sout 511 (255) n (n+255) n+1 (n+256) 253 (509) 254 (510) 255 (511) n+2 (n+257) yi+255 (yi) high-z low row sam start address yi t cah t ral t rad t sca t soh t soh t sca valid sout t crp t crp
hm538123b series 42 split write transfer cycle t rc ras cas address we i/o (output) dt/oe dsf se si/o (output) qsf si/o (input) sc t ras t rp t csh t rsh t rcd t cas t asc t rah t asr t ws t wh t off1 t dts t dth t fsr t rfh t rst t ast t cst t scc t sc t scp t sts t sis t sih t sis t sih t sqd t sqh t sqd t sqh sam address msb valid sin valid sin valid sin valid sin valid sin valid sin 511 (255) n (n+255) n+1 (n+256) 254 (510) 255 (511) n+2 (n+257) yi+255 (yi) high-z low row sam start address yi t cah t ral t sis t sih valid sin n+3 (n+258)
hm538123b series 43 serial read cycle se sc si/o (output) t scc t scp t sc t sca t soh t sez t sc t scp t sc t sea t sca t scp t sc t sca t soh valid sout valid sout valid sout valid sout t scc t scc serial write cycle se sc si/o (input) valid sin valid sin valid sin t swh t swis t swih t sws t scc t sc t scp t sis t sih t scc t scp t sc t scc t sc t scp t sc t sis t sih t sih t sis
hm538123b series 44 package dimensions hm538123bj series (cp-40d) 9.40 0.25 1 20 0.10 0.43 0.10 3.50 0.26 + 0.31 ?0.14 2.30 21 40 26.16 max 25.80 0.74 10.16 0.13 11.18 0.13 1.30 max 1.27 + 0.25 ?0.17 0.80 hitachi code jedec eiaj weight (reference value) cp-40d conforms 1.73 g 0.41 0.08 unit: mm dimension including the plating thickness base material dimension
hm538123b series 45 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications.
hm538123b series 46 revision record rev. date contents of modification drawn by approved by 1 mar.18, 1994 initial issue m. takahashi t. kizaki 2.0 dec.8, 1994 addition of figure 4: example of row bit data transfer addition of description about figure 4 for write transfer cycle m. takahashi t. kizaki 3.0 apr. 24, 1995 ac chracteristics addition of t sdd2 (min): 25/25/25/25 ns addition of notes 17 timing waveforms read transfer cycle addition of t sdd2 timing addition of notes 3 m. takahashi t. kizaki 4.0 nov. 1997 change of subtitle

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